The slow growth of the number of pins per package coupled with increasing device densities is leading to decreasing off-chip memory bandwidth per core which in turn leads to reductions in system level performance. In this work we present a 2-tier stacked IC structure, referred to as the Short-Stack, to push back this pin bandwidth wall. The Short-Stack consists of a processor die of multiple cores in the bottom tier, and a multi-banked last level cache (LLC) die including the memory controllers and network-on-chip (NoC) in the top tier, face-to-face bonded with the processor tier. We characterize the timing delay, power consumption, and density of an eDRAM implementation of the LLC, and consider a range of LLC designs using SRAM and eDRAM. Using a full-system, cycle-level simulator, we conduct a quantitative analysis of a 16-core Short-Stack executing SPLASH-2 benchmarks. We present performance results in comparison to i) a traditional 2D processor implementation and ii) a multi-tier 3D package with stacked DRAM memory in terms of performance, power and energy efficiency.

Short-Stack: Pushing Back the Pin Bandwidth Wall with FinFET-based eDRAM In-Package Last Level Cache [PDF]