A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems
Zhenjiang Dong, Jun Wang, George Riley, Sudhakar Yalamanchili. “A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems.” IEEE 21st International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS’13). August 2013.
Abstract
There has been little research that studies the effect of partitioning on parallel simulation of multicore systems. This paper presents our study of this important problem in the context of Null-message-based synchronization algorithm
for parallel multicore simulation. This paper focuses on coarse grain parallel simulation where each core and its cache slices are modeled within a single logical process (LP) and different partitioning schemes are only applied to the interconnection network. In this paper we show that encapsulating the entire on-chip interconnection network into a single logical process is an impediment to scalable simulation. This baseline partitioning and two other schemes are investigated. Experiments are conducted on a subset of the PARSEC benchmarks with 16-, 32-, 64- and 128-core models. Results show that the partitioning scheme has a significant impact on simulation performance and parallel efficiency. Beyond a certain system scale, one scheme consistently outperforms the other two schemes, and the performance as well as efficiency gaps increases as the size of the model increases – with up to 4.1 times faster speed and 277% better efficiency for 128-core models. We explain the reasons for this behavior, which can be traced to the features of the Null-message-based synchronization algorithm. Because of this, we believe that, if a component has increasing number
of inter-LP interactions with increasing system size, such components should be partitioned into several sub-components to achieve better performance.
for parallel multicore simulation. This paper focuses on coarse grain parallel simulation where each core and its cache slices are modeled within a single logical process (LP) and different partitioning schemes are only applied to the interconnection network. In this paper we show that encapsulating the entire on-chip interconnection network into a single logical process is an impediment to scalable simulation. This baseline partitioning and two other schemes are investigated. Experiments are conducted on a subset of the PARSEC benchmarks with 16-, 32-, 64- and 128-core models. Results show that the partitioning scheme has a significant impact on simulation performance and parallel efficiency. Beyond a certain system scale, one scheme consistently outperforms the other two schemes, and the performance as well as efficiency gaps increases as the size of the model increases – with up to 4.1 times faster speed and 277% better efficiency for 128-core models. We explain the reasons for this behavior, which can be traced to the features of the Null-message-based synchronization algorithm. Because of this, we believe that, if a component has increasing number
of inter-LP interactions with increasing system size, such components should be partitioned into several sub-components to achieve better performance.
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Citation
@inproceedings{mascots13-dong,
author={Zhenjiang Dong, Jun Wang, George Riley, Sudhakar Yalamanchili},
booktitle={IEEE 21st International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS’13)},
title={A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems},
year={2013},
month={August},
}
author={Zhenjiang Dong, Jun Wang, George Riley, Sudhakar Yalamanchili},
booktitle={IEEE 21st International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS’13)},
title={A Study of the Effect of Partitioning on Parallel Simulation of Multicore Systems},
year={2013},
month={August},
}
