Congratulations to Chad for successfully defending his PhD proposal titled “Accelerator Architecture Modeling with a Pipeline-Oriented Hardware Description Language” !

By exploiting the equivalence between multithreaded software and pipelined hardware, we can quickly construct, model, and analyze a range of both fixed function and instruction set accelerators well-suited to the energy constraints of modern architectures. This is reached by (1) realization of a domain specific language that provides for the high-productivity, high-performance modeling of pipelined accelerators by exploiting the equivalence of these accelerators with multithreaded software execution, (2) implementation of a range of fixed-function and general purpose accelerators, (3) automatically-generated area, energy, and fault models of these accelerators, and (4) evaluation of these accelerators in the context of near-memory processing.