The paper “A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective” Selected as the 2014 IEEE Circuits and Systems Society Very Large Scale Integrated Systems Best Paper

Professors Sudhakar Yalamanchili and Saibal Mukhopadhyay and their recently graduated students, Subho Chatterjee and Mitchelle Rasquinha, received the 2014 IEEE Circuits and Systems Society Very Large Scale Integrated Systems Best Paper Award for their paper “Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective”.

Spin-Torque-Transfer RAM (STTRAM) is an emerging non-volatile memory technology that can retain information with practically no energy loss; it has the potential to dramatically transform the energy landscape of future computing systems. However, to realize the energy-efficiency potential of STTRAM in designing energy-efficient processing architectures, the interactions between the unique device physics of STTRAM, processor architecture, and the applications must be understood. This paper presents a modeling and analysis framework that can be used to understand these interactions, particularly from an energy perspective. The framework uses this understanding to explore the circuit-architecture design space of this emerging memory technology for the design of energy-efficient memory hierarchies in modern processors. The work presented in this paper was supported by the National Science Foundation and Intel Corporation.

Congratulations to all the authors!