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Congratulations to Jin Wang on successfully defending her PhD thesis titled “Acceleration and Optimization of Dynamic Parallelism for Irregular Applications on GPUs”!

Posted by on Nov 7, 2016 in News | 0 comments

Jin Wang successfully defended her thesis titled “Acceleration and Optimization of Dynamic Parallelism for Irregular Applications on GPUs” on Nov 7, 2016. Congratulations Dr. Wang!!! Abstract: The objective of this thesis is the development, implementation and optimization of a GPU execution model extension that efficiently supports time-varying, nested, fine-grained dynamic parallelism occurring in the irregular data intensive applications. These dynamically formed pockets of structured parallelism can utilize the recently introduced device-side nested kernel launch capabilities...

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Congratulations to Eric Anger on getting his paper accepted in E2SC 2016!

Posted by on Nov 7, 2016 in News | 0 comments

Eric’s paper “Power-Constrained Performance Scheduling of Data Parallel Tasks,” co-authored with Jeremiah Wilke, and Sudhakar Yalamanchili was accepted in Energy Efficient Supercomputing Workshop (E2SC), 2016. Congratulations!!!

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Congratulations to Karthik on getting his paper accepted at HPCA 2017!

Posted by on Nov 7, 2016 in News | 0 comments

Karthik’s paper “Application-Specific Performance-Aware Energy Optimization on Android Mobile Devices”, co-authored with Jun Wang, Sudhakar Yalamanchili, Yorai Wardi and Handong Ye was accepted by HPCA 2017. Congratulations!!!  

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Neurocube (ISCA 2016 paper) makes the news!

Posted by on Sep 22, 2016 in News | 0 comments

Congratulations to the GREEN lab team and Dr. Yalamanchili! Find the news article here: http://www.nextplatform.com/2016/09/12/deep-learning-architectures-hinge-hybrid-memory-cube/ The ISCA paper abstract: This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory...

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Congratulations to Eric Anger on successfully defending his PhD proposal “Application-level Modeling and Analysis of Time and Energy for Optimizing Power-constrained Extreme-scale Applications”

Posted by on Aug 31, 2016 in News | 0 comments

The objective of the proposed research is to create a methodology for the modeling and characterization of extreme-scale applications operating within power limitations in order to guide optimization. It is likely that forthcoming high-performance machines will operate with stringent power caps, tying the performance of the systems to their energy-efficiency. Optimizing extreme-scale applications to operate within power limitations will require new techniques for understanding the relationships between application characterization, performance, and energy. The main contributions of this work...

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Congratulations to Minhaj Hassan on successfully defending his PhD thesis “Exploiting On-Chip Memory Concurrency in 3D Manycore Architectures”

Posted by on Aug 31, 2016 in News | 0 comments

Many congratulations Dr. Hassan! The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the need for re-optimization in the presence of this increase in concurrency of the memory system. First, we observe that 2D network latency and inefficient parallelism management in the current 3D designs are the main bottlenecks to fully exploit the...

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