News

Neurocube (ISCA 2016 paper) makes the news!

Posted by on Sep 22, 2016 in News | 0 comments

Congratulations to the GREEN lab team and Dr. Yalamanchili! Find the news article here: http://www.nextplatform.com/2016/09/12/deep-learning-architectures-hinge-hybrid-memory-cube/ The ISCA paper abstract: This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory...

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Congratulations to Eric Anger on successfully defending his PhD proposal “Application-level Modeling and Analysis of Time and Energy for Optimizing Power-constrained Extreme-scale Applications”

Posted by on Aug 31, 2016 in News | 0 comments

The objective of the proposed research is to create a methodology for the modeling and characterization of extreme-scale applications operating within power limitations in order to guide optimization. It is likely that forthcoming high-performance machines will operate with stringent power caps, tying the performance of the systems to their energy-efficiency. Optimizing extreme-scale applications to operate within power limitations will require new techniques for understanding the relationships between application characterization, performance, and energy. The main contributions of this work...

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Congratulations to Minhaj Hassan on successfully defending his PhD thesis “Exploiting On-Chip Memory Concurrency in 3D Manycore Architectures”

Posted by on Aug 31, 2016 in News | 0 comments

Many congratulations Dr. Hassan! The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the need for re-optimization in the presence of this increase in concurrency of the memory system. First, we observe that 2D network latency and inefficient parallelism management in the current 3D designs are the main bottlenecks to fully exploit the...

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Congratulations to Si Li, William Song and Minhaj Hassan for their papers accepted by IEEE International Reliability Physics Symposium!

Posted by on Apr 18, 2016 in News | 0 comments

Paper “Software-based Dynamic Reliability Management for GPU Applications”, co-authored by Si Li, Vilas Sridharan, Sudhanva Gurumurthi and Sudhakar Yalamanchili, has been accepted by IEEE International Reliability Physics Symposium. Congratulations to Si! Paper “Reliability-Performance Tradeoff between 2.5D and 3D-Stacked DRAM Processors”, co-authored by William J. Song, Syed Minhaj Hassan, Saibal Mukhopadhyay and Sudhakar Yalamanchili, has been accepted by IEEE International Reliability Physics Symposium as a short paper/poster. Congratulations to William and...

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Prof. Yalamanchili gave a keynote “Implications of Memory-Centric Computing Architectures for Future NoCs” at the 9th International Symposium on Networks-on-Chip (NOCS).

Posted by on Jan 10, 2016 in News | 0 comments

The keynote “Implications of Memory-Centric Computing Architectures for Future NoCs” was presented by Prof. Yalamanchili at the 9th International Symposium on Networks-on-Chip (NOCS) in Vancouver, Canada on September 29.

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Paper “General-Purpose Join Algorithms for Large Graph Triangle Listing on Heterogeneous Systems” accepted by GPGPU-9.

Posted by on Jan 10, 2016 in News | 0 comments

The paper “General-Purpose Join Algorithms for Large Graph Triangle Listing on Heterogeneous Systems”, co-authored by Daniel Zinn, Haicheng Wu, Jin Wang, Molham Aref and Sudhakar Yalamanchili, was accepted by GPGPU-9. This was a collaborative work with LogicBlox. Congratulations to the authors!

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